The present invention is generally related to wireless communications, and is particularly related to transmit frequency signal generation.
In “direct conversion” transmitters, transmitter modulation and frequency up-conversion generally occur in the same circuit, which means that the transmitted carrier frequency signal is the same as the local oscillator (LO) frequency. While this approach offers economic advantages in terms of circuit simplification and reduced component count, it poses certain design challenges.
For example, the loop bandwidth of the direct-conversion frequency synthesizer generally should be kept relatively narrow in the interest of suppressing sideband phase noise for good Adjacent Channel Power (ACP) suppression performance. However, the relatively low power, high tuning sensitivity Voltage Control Oscillators (VCOs) used in such frequency synthesis loops are prone to frequency pulling, wherein they are disturbed by the modulations of the relatively high-power transmit signal.
Increasing the loop bandwidth of the frequency synthesizer improves its resistance to pulling, but decreases its ability to suppress sideband phase noise. As such, improving pulling resistance and ACP noise performance represent competing design challenges that are difficult to reconcile in single-loop direct-conversion architectures. “Two-step” transmitter architectures may be used to reconcile the above conflict between pulling resistance and ACP performance, by up-converting the base band information signal to be transmitted using two frequency conversion steps, so that the power amplifier output spectrum is relatively far away from the VCO operating frequencies.
However, as a general proposition, the second up-conversion step generates unwanted sidebands and spurious frequencies that must be significantly suppressed using a relatively expensive high-Q filter. Because such filters are difficult to integrate on-chip in high-density circuits, the two-step conversion process ordinarily necessitates the use of off-chip filters, adding to circuit expense and size.
Further, it is known to use a translational loop architecture to mitigate VCO injection pulling issues, wherein a main phase locked loop operates as a primary LO frequency to a frequency mixer in the translational loop and a secondary LO frequency is applied to the translational loop's phase detector to enable phase comparison with the translated signal. However, an additional VCO and phase locked loop circuitry (e.g., phase detector, programmable frequency dividers, loop filter) generally are necessary to generate the second LO frequency to obtain the necessary offset (intermediate) frequencies, which adds to the cost and size of the design.